1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit including power through silicon vias (TSV)s.
2. Related Art
In recent semiconductor devices, technology for stacking a plurality of semiconductor integrated circuits is being adopted. To achieve high performance while providing a reduction in the size of electrical/electronic products, various techniques for fabricating a stacked package are being developed.
A stacked package in the semiconductor industry field refers to two or more semiconductor chips or packages that are vertically piled up (i.e. stacked vertically). In accordance with this stacked package, for example, a semiconductor memory device can be implemented to have a memory capacity that is twice or more than the memory capacity that can otherwise be achieved for a given chip area using a given semiconductor process technology. Furthermore, the stacked package is advantageous over standard packages in that the memory capacity can be increased while keeping the circuit board mounting area and mounting area efficiency of the device relatively unchanged. Thus, research and development for manufacturing stacked packages are being accelerated.
A stacked package can be fabricated by using a method of stacking pre-packaged semiconductor chips and then packaging the stacked semiconductor chips at once, or by using a method of stacking post-packaged semiconductor chips. The semiconductor chips of a stacked package can be electrically coupled together by using metal wires or by using through silicon vias (TSVs). In particular, a stacked package using the through silicon vias approach has a structure in which the through silicon vias are formed within the semiconductor chips, and the semiconductor chips are vertically coupled using the through silicon vias to physically and electrically connect the semiconductor chips.
A semiconductor device can include distinct regions which can be classified as an active region that includes active circuitry such as memory banks, or a peripheral region that includes pads for interfacing signals and power to other devices.
FIG. 1 is a diagram showing an example arrangement of a semiconductor device. As shown in FIG. 1, the semiconductor device includes a plurality of power lines VDD 1 and VSS 2.
The power lines 1, which are spaced apart from each other, are coupled by metal lines so that power lines 1 have the same VDD voltage potential. Similarly, the power lines 2, which are spaced apart from each other, are coupled by metal lines so that power lines 2 have the same VSS voltage potential. Furthermore, a plurality of cap regions 3 is included between the power lines 1 and 2. Each of the cap regions 3 implements a reservoir capacitor.
A reservoir capacitor functions to compensate for the unstable supply of power due to the parasitic capacitance of a power source. More particularly, the reservoir capacitor can stabilize a power source because the reservoir capacitor provides durability and solidarity against the shaking of the power source and/or various noises on the power signal.
Meanwhile, a dummy region 4 is disposed between the cap regions 3.
The dummy region 4 is a region that includes dummy metal lines. The metal lines within the dummy region 4 are assumed to be in a floating or unconnected state.
Signal TSVs S and power TSVs P are disposed under the region where power lines 1 and 2 run (i.e. outside the active region). The region in which the signal TSVs S and the power TSVs P are disposed is a pad region (i.e. part of the peripheral region where pads are disposed).
In a semiconductor device such as the one described above, the intensity of a power source decreases gradually according to the number of stacked semiconductor chips. FIG. 2 is a perspective view showing that the intensity of a power source voltage is reduced according to an increase in the number of stacked semiconductor chips. In other words, the intensity of power at each incrementally stacked semiconductor chip becomes less and less.
Accordingly, it is desirable to supply a stable and consistent power supply to each semiconductor chip when a plurality of semiconductor chips is stacked.